1. Field of the Invention
The present invention relates in general to transistor amplifiers and in particular to an F.sub.t doubler amplifier having a low-power biasing circuit.
2. Description of Related Art
Minority carrier charge storage in a bipolar transistor's base region causes it to behave electrically as a capacitor between its base and its emitter. This capacitance causes the transistor's current gain to decrease as the frequency of an input signal applied to its base increases.
The current gain of a transistor amplifier rolls off rapidly at higher input signal frequencies. The frequency at which the short circuit current gain of an amplifier falls to unity is commonly called the "current gain bandwidth" (F.sub.t) of the amplifier. It is used as a measure of the ability of an amplifier to provide a combination of bandwidth and current gain. Thus amplifier design is a tradeoff between gain and bandwidth, and an amplifier having a higher F.sub.t gives a circuit designer more flexibility when making that tradeoff.
FIG. 1 illustrates a well-known "F.sub.t doubler" amplifier 10 employing two identical differential amplifier stages 12 and 14 arranged to amplify an input current I.sub.IN to produce an output current I.sub.OUT with twice the F.sub.t of a single-stage amplifier. Thus for example, amplifier 10 could provide approximately twice the current gain at a given bandwidth or approximately twice the bandwidth for a given current gain.
Amplifier stage 12 includes two transistors Q1 and Q2 having emitters linked by a resistor R1 and coupled to ground through biasing current sources I1 and I2. Identical differential amplifier stage 14 includes two transistors Q3 and Q4 having emitters linked by a resistor R2 and coupled to ground through biasing current sources I3 and I4. Resistors R7 and R8 bias bases of transistors Q1 and Q4, and bases of transistors Q2 and Q3 are interconnected. Amplifier stages 12 and 14 thus have inputs connected in series such that an input current signal I.sub.IN passes through both amplifier stage inputs. Thus each amplifier stage amplifies the same input current. The amplifier output differential currents I.sub.OUT appear at the interconnected collectors of transistors Q1 and Q3 and the interconnected collectors of transistors Q2 and Q4. Since the outputs (transistor collectors) of the two stages connected in parallel, their output currents are summed to produce I.sub.OUT. Hence the current gain bandwidth of the two-stage amplifier 10 is twice that of an amplifier employing only a single stage.
When all transistors Q1-Q4 are properly biased, each stage operates with maximum dynamic range. One practical difficulty in implementing the amplifier circuit of FIG. 1 is in properly biasing the bases of transistors Q2 and Q3 to provide a bias voltage V3 that is equal to the common mode average of voltages V1 and V2 at the bases of transistor Q1 and Q4.
Some prior art F.sub.t doubler amplifier circuits use a simple voltage source 16 to bias the bases of transistors Q2 and Q3 to the correct bias voltage V3. To properly adjust the output voltage of source 16 it is necessary to accurately predict base voltages V1 and V2, but it is often not easy to do that.
FIG. 2 illustrates a prior art F.sub.t doubler amplifier employing a biasing circuit 18 that senses V1 and V2 and automatically generates the correct bias voltage V3 at the bases of transistors Q2 and Q3. Bias circuit 18 includes two resistors R3 and R4 and a unity (voltage) gain feedback amplifier 20. The matching resistors R3 and R4 connected in series between the bases of transistors Q1 and Q4 act as a voltage divider to produce the necessary bias voltage V3=(V1+V2)/2 at the bases of transistors Q2 and Q3. The amplifier 20 isolates the bases of transistors Q2 and Q3 from resistors R3 and R4. If amplifier 20 were omitted so that R3 and R4 were directly connected to the bases of Q2 and Q3, the combined base bias current I.sub.B drawn by transistors Q2 and Q3 would be supplied through resistors R3 and R4. This would increase the voltage drops across resistors R3 and R4, thereby lowering the magnitude of V3 below the desired level. Since amplifier 20 has a high input impedance, it can supply the necessary base current I.sub.B while drawing little current through resistors R3 and R4, thereby maintaining V3 at the proper biasing level. One drawback to amplifier 20 is that since it is a feedback amplifier driving a capacitive load, it may be subject to instability under some conditions.
Nonetheless, the two-stage "F.sub.T doubler" amplifier of FIG. 2 is used in many applications. However it is not practical to expand the amplifier to include more than two stages so as to further multiply the F.sub.T of the amplifier. In the two-stage implementation illustrated in FIG. 2, the bias voltage V3 is substantially constant because it is the average of opposing two ends of a differential signal. Hence unity gain amplifier 20 amplifies a DC signal. If we were to expand the two-stage amplifier to include more than two stages, then the bias voltages that a set of unity-gain amplifiers would have to supply to junctions between successive stages would have to oscillate with the same frequency as the input signal because they would not be the common mode average of two ends of a differential signal. Thus the unity gain amplifiers would have be able to operate at impractically high frequencies.
What is needed is a simple, low-power circuit for automatically biasing the bases of transistors in an F.sub.T multiplier amplifier that is stable under all conditions and which permits the amplifier to employ more than two stages.